ASIC Digital Verification Engineer Lead

Position: ASIC Digital Verification Engineer Lead
Location: Yokohama
Language: N2 and above

Job Description:

Looking for 8+ yrs of design verification Engineers with below skills

• RTL design (Verilog HDL)
• EDA verification experience (NC Verilog)
• Ability to use Microsoft Office software (Excel, Word, Outlook)
• Ability to use Linux CUI commands
• Experience with SV, UVM and SystemVerilog Assertions (SVA)
• Experience using version control tools (Subversion, git)

Knowledge that would be beneficial

• AI Insights
• Ability to check timing reports during implementation

Roles & Responsibilities

• Under general supervision, performs engineering work and applied
  research, development, and design of new Integrated Chips.
• Work includeクイーン カジノrchitectural Design, Logic Design, Circuit Design,
  Physical Design, Verification, Fabrication, Packaging of Chips